[sdiy] S&H problems

[Grant Richter]

OK a couple of tips:

> I'm currently trying to put together a sample and hold circuit, I'm not
> having any trouble getting it to sample, but I'm quite struggling with
> the  holding end of things!

You and every who ever built a sample and hold, welcome to the club.
> 
> Seems to me that the trouble is in the switch, it's obviously leaking
> back through the switch. I'm using a JFET, The drain is the output,
> source as the input. I have a 1M resistor connected between the source
> and gate. As well, I have a diode connected with the anode connected to
> the JFET gate and the cathode is the controller input terminal.
> 
> Both the input and output are buffered, which leads me to suspect that
> the leakage is through the gate, but I have not confirmed this. This is
> backed up by the fact that when I tried removing the source connection
> before closing the switch, the capacitor still discharged.
> 

An N-channel JFET gate needs to be pulled more negative than any other
terminal on the device (that's what the diode is for). To completely shut it
off, it has to be pulled more negative by the amount of the pinch off
voltage. To turn it on, you just let the gate float up to the voltage of the
source terminal (that's what the 1 Meg is for).

Every op-amp or voltage buffer has to draw SOME bias current (or leakage).
The voltage buffer on the cap HAS to be a FET low bias current type like a
TL08x or a CA3140. A 741 or LM324 will NOT work. Also, use a big enough cap
for the sample cap. 0.01uF or 10,000pF is a good compromise between hold
time and sample time.

See the data sheet for the LF398 sample and hold chip.

http://www.national.com/pf/LF/LF398.html

The chip is so cheap and easy, it make sense to just use them unless you
need some special features (like slew rate limiting inside the S/H for
probability control).
Try Jameco, Mouser etc.