[sdiy] SSM2040 filter question

[René Schmitz]

Hi Antti and List,

I think there is nothing wrong with the simulation.

This nonlinearity is there, but you will only see it in certain 
occasions. For example when you plot the DC transfer of the cell. Or if 
the current through the gain cell is high, so that there is practically 
no integration going on in the cell. (Or rather, there is enough current 
available, so that the cap can follow the distorted input waveform.) The 
cap can reach the voltage compliance (about -0.8V) of the sinking "OTA" 
circuit, and the integrated current goes to zero. That makes sense, 
because if there were still current flowing, the cap would change its 
voltage. But its hanging at the clipping level.

I think in the other case, where there is little current available, the 
cap gets charged and discharged unequally, thus generating a DC offset, 
which by the negative feedback steers the cell back towards the linear 
operating region.

The amount of current depends on frequency of course, I mean "little" 
when the cell is delimiting the slew rate of the output signal. Or 
another way to put it is if the signal frequency is below the corner 
frequency.


An interesting aside is that the filter is composed out of inverting 
stages. That means that each half wave of the input signal will undergo 
that "clipped integration", only in different parts of the circuit. That 
would mean that in total, both halfes will be clipped. A circuit with 
only noninverting stages, would be an interesting variation.

Cheers,
  René


-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159