Odp: [sdiy] Latch-up question

[Roman Sowa]

yes, -11V should be safe, and I bet -12.5V would also
work fine depending on IC used. That's assuming TL is
powered from +whatever, -15V.
Phase reversal starts when input stage is not properly
biased. Having p-FET inputs, TL07x needs couple of
volts above -Vss to bias them. OTOH just because
of that there's no limit for upper voltage.
And since datasheet specifies differential input voltage
at +/-30V (which means there are no clamping diodes)
 TL should work fine even at (-) at +14.4V and (+) at -11V

Roman
 
----- Original Message ----- 
From: fmg <1984 at softhome.net>
To: <synth-diy at dropmix.xs4all.nl>
Sent: Saturday, November 01, 2003 4:42 AM
Subject: [sdiy] Latch-up question


> Hi all
> 
> I'm working in an adsr-r/env_gen and am facing the posibility
> of phase-reversal issue in one (or two) of TL08x I included
> in the design.
> 
> What follows is an excerpt of National's AN447:
> 
> >"In open-loop operation (i.e., no feedback from output to in-
> >verting input, or, during any time that the opamp is slew-rate
> >limited), taking the non-inverting input below the inverting
> >input causes the output to slew toward the negative supply
> >rail. If the voltage at the non-inverting input is more negative
> >than the negative common-mode limit, the input stage ceas-
> >es to function properly and the output swings to its positive
> >limit. This apparent ``phase-reversal'' is temporary; bringing
> >the non-inverting input back within the legal input common-
> >mode range restores the part's normal operation."
> 
> Now, wich is the "negative common-mode limit" ?
> 
> In the TL081 datasheet is spec'ed:
> 
> >Differential Input Voltage +/-30V
> >
> >Parameter           Condition       Min        Typ
> >------------------------------------------------------------
> >Input Common-Mode       Vs +/-15V     +/-11V    +15V/-12V
> >Voltage Range
> 
> Should I consider -11V the limit for the non-inverting input to
> be in a safe area from latch-up?
> 
> ...even if the inverting input is at a diode below Vdd (+14.4V) ?
> 
> Are these assumptions wrong?
> 
> 
> I'll appreciate any comments about.
> 
> Thanks,
> 
> Fabio Gonzalez