[sdiy] op amp phase inversion

[Czech Martin]

my (perhaps limited) understanding is that e.g. in a npn
input stage the base will get positive until it reaches
collector potential. Up to this point the collector
will drop when the base rises. But a further rising
base will forward bias the base collector diode,
thus effectively rising the collector again
(that old Moog rectifier schematic).

It is the other way arround for pnp inputs.

For a jfet I assume nothing will happen, until
the gate implantation is forward biased.
In this case we see a forward biased diode
plus some strange parallel bipolar transistor
and maybe some vertical current in the substrate.


I found a few (older) bipolar types mentioned with latch
up in the op amp cookbook by Jung.

m.c.

-----Original Message-----
From: jhaible at debitel.net [mailto:jhaible at debitel.net]
Sent: Montag, 26. Mai 2003 13:04
To: Czech Martin
Cc: Sdiy (E-mail)
Subject: Re: [sdiy] op amp phase inversion


> The explanation applied to bipolar input stages. But JFET op amps
> can show this behaviour as well. 

I thought JFET opamps were especially prone to this phase reversal effect.


> From the datasheet one can not really tell if the op amp will latch or 
> not. E.g. I could not see a problem in the TL071 data sheet,
> nevertheless, the device will latch 

You can bet that, if the data sheet does not explicitely scream
"this uses a special design to avoid phase reversal", then the
opamp will probably do it.

JH.

-------------------------------------------------
debitel.net Webmail