[sdiy] Parallel processing clock design question

[Magnus Danielson]

From: Tim Ressel <madhun2001 at yahoo.com>
Subject: Re: [sdiy] Parallel processing clock design question
Date: Sun, 13 Jul 2003 15:32:24 -0700 (PDT)

> I used to work for Ametek CRD. They were building
> parallel 68020 machines based on Caltech's wormhole
> messaging strategy. It's amazing how two fast new
> Pentiums can outrun 1024 of the 25MHz 68020s we were
> using!

Which reminds me... back at home (I am in my summerhousr right now) I have
4 CPU boards from HP 9000/320 and 1 CPU board from HP 900/310 (I think I have
the HP numbering correct). The first CPU boards have a 25 MHz 68020 and a
20 MHz 68882 (FPU) and the later is a 20 MHz 68020 and 15 MHz 68882. They both
have cache-memories as I recall it. I have been given them and my plans for
them is to wire up a bus and run them in parallel. The smaller CPU-board as a
front-end type of processing and the 4 others as basically DSPs for well...
some kind of wierd sound-app. I would then make a board with main-memory,
IDE-controller, MIDI, keyboard, maybe some video, sound in and out both analog
and digital. Doesn't it sound like a fun project? 

Sure, a scap-yard PC outperform it these days, but THAT IS NOT THE POINT!

I will probably put a 10 MHz reference-clock input on it. All gear should
have one. Propper timing all over the place is my melody.

Cheers,
Magnus