[sdiy] Parallel processing clock design question

[James Patchell]

No, this was a computer I did for Lockheed back in....about 1987 I 
think.  The processors it used were Geometric Array Parallel Processors 
(GAPP).  I was involved with a Polish Mathematician (Holstinsky...I think 
that is how you spell his name) who came up with the idea for both the GAPP 
chips and also the micro code sequencer that run the whole thing (it was a 
Distributed Micro Code sequencer, or DMC for short)...it was a SIMD type 
machine that was used to process video.  It could locate an object in a 
picture in something like 5uSec, which was pretty danged fast back 
then.  Funny thing is, you could probably build the whole thing inside of a 
couple of Virtex FPGA chips now...at a much higher clock rate (the machine 
ran at 10MHz that I built).

         -Jim

At 05:48 PM 7/12/2003 -0700, John L Marshall wrote:
>Jim,
>
>Did you work for n-Cube?
>
>Take care,
>John
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>
>Pacific Northwest Synthesizer Meeting
>
>DATE CHANGE: August 2, 2003
>
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>------------------------------------------------------------------
>
>----- Original Message -----
>From: "James Patchell" <patchell at cox.net>
>To: "jbv" <jbv.silences at club-internet.fr>; "SynthDIY"
><synth-diy at dropmix.xs4all.nl>
>Sent: Saturday, July 12, 2003 1:43 PM
>Subject: Re: [sdiy] Parallel processing clock design question
>
>
> >          It is best to use a clock source, such as a oscillator, that can
> > drive into the characteristic impeadence of the traces on your PC
> > board.  You then route the clock as a single continuous line, preferably
> > not through any vias with a terminator on the end.  I have found this
> > methode a pretty good one for routing clocks.  I used this in a system I
> > did that had 12,000 uP chips in it running in parrallel.
> >
> >          -Jim
> >
> >
> > At 10:32 PM 7/12/2003 +0100, jbv wrote:
> > >Hi again,
> > >
> > >Let's say I want several (2 to 5) uCs to run in
> > >parallel (yes, this is related to the recent thread
> > >"sound synthesis with uC") at high speed (40 /
> > >50 MHz or more).
> > >
> > >What is the best solution for clock design :
> > >
> > >1) use only 1 Xtal, which means rather long
> > >connections between Xtal and each uC clk
> > >input
> > >
> > >2) use 1 Xtal per uC, which means more parts
> > >and more PCB room but smaller connections
> > >
> > >3) use only 1 Xtal, but at lower freq and hook
> > >each uC clk input with a freq multiplier
> > >
> > >4) use another smarter solution that hasn't
> > >crossed my mind yet but that will be submited
> > >by some smart list member any time soon...
> > >
> > >Thanks in advance,
> > >JB
> >
> >