[sdiy] PAIA VC-EG Questions

[greg montalbano]

At 05:33 AM 1/21/03 -0500, you wrote:
>     Hey you guys. I'm finally wiring up an old Paia VC-EG board I have. Its
>the EKx-10 to be exact (based around a CEM 3310). There's a couple of
>questions I have that's holding me back....
>
>     There are 2 solder pads each for ATTACK, DECAY, RELEASE. There's one pad
>for SUSTAIN. I know each set of these pads gets a jack, right? The SUSTAIN
>must get either a jack or a pot. I dont know which though.

There are two pads for A, D & R so that you can hook up an initial value 
pot for each, and also have a jack input for external control voltages.
SUSTAIN traditionally just goes to a level-control pot.


>     Another thing thats got me all confusd are the four pads labeled "A" "B"
>"C" and "L". The documentation says that A-C are,
>
>"summing nodes for control voltages. If desired, additional summing
>resistors may terminate at these nodes to provide more control voltage
>inputs." Could these just be duplicate control voltage inputs? I was
>assuming the main CV inputs were located on the edge of the card (PCB).

They are; but this just gives you access to the control summers in the 
event that the two edge connectors for each summing amp aren't enough for 
your fevered creation.

>It
>goes on to say:
>
>"L is the CEM 3310's ATTACK OUT pin and may be used to generate an attack
>phase logic signal as outlined in the CEM 3310 data sheet."
>
>     Could this pin be used as an "end of cycle" trigger?

That, I'm afraid I don't recall (don't have the data sheets here with 
me;  but they should tell you what you need to know).

~GMM