[sdiy] expo accuracy? or integrator accuracy?, or both?

[René Schmitz]

Hi Ian et al. 

>Good idea.  Another trick that can help track down drift sources is to 
>apply heat locally, although that won't separate the different effects 
>within an opamp, of course.

Right. One could use quad (or hex) packages and heat up the die using the 
other amplifiers.

>Agreed.  I especially appreciate the reminder that the discharge switch 
>leakage can easily obviate the advantages of a low leakage op amp 
>integrater.  Your use of the two-FET trick in your VCO 3 gives a good way 
>to attack that problem.  How much residual leakage you get with that 
>approach and how it depends on temperature is not obvious to me, since 
>leakage is usually speced at a very high voltage. This could be looked at 
>further.

Well, the frequency after which the oscillator just stops is about 1/15
minutes. With the integrating cap and a voltage sweep of 5V I calculated 
about 12pA of residual leakage. That is comprised out of the gate source 
leakage of the FETs (essentially that of a back biassed diode), the D-S 
leakage (although I feel that this will be very tiny), the amplifier input 
bias, the leakage current of the cap and the leakage of the expo 
converter. (And maybe also some leakage effects due to solder flux.) 
Of course it is difficult to break up this figure into its sources, 
especially since I suspect that some of the currents are of opposite sign. 

This makes me think that a mosfet for the switch that is closer to the 
summing input could make a difference. Its gate would be at 0V when off, 
unlike the one of the jfet, so this should reduce the leakage even 
further. Maybe by doing so one can get a grip on the magnitude of that 
reverse leakage.

Cheers,
 René






-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159