linear FM : was RE: [sdiy] Temperature Compensated VCO attempt - help?

[Magnus Danielson]

From: René Schmitz <uzs159 at uni-bonn.de>
Subject: Re: linear FM : was RE: [sdiy] Temperature Compensated VCO attempt - help?
Date: Tue, 04 Feb 2003 21:41:36 +0100

Dear René,

> >One way of solving the issue is to have the linear FM bandwidth limited (to
> >say 20kHz or something) and toss in a slight hysteresis for the upper and lower
> >limit comparators, enought to ensure you get long enought pulses. Then you
> >should basically be home free.
> 
> The problem lies in the nondeterminism: What do you do if the FM signal
> changes its sign during that pulse?

My point was actually this (sorry for not articulating the idea but concentrate
on the solutions):

You have to work with probabilities. As soon as you talk quantization into
definite states or values you really just run a game in probability. In digital
telecommunication we talk stuff like Bit Error Rate (usually just refered to as
BER) and jitter (originally the part of the phase noise which only affects the
sampling of single bits, wander is what requires multiple-bit elastic buffers).
These are connected, so that a certain amount of jitter can be converted to
represent a certain BER factor. Speciallized instruments helps to analyse this
and tune the receiver towards optimum BER performance given the jitter in the
signal.

Many data and telecom systems is designed to normally have a BER of 10^-12.
Examples are Fibre Channel and Gigabit Ethernet (which BTW copied a little too
frisky from the Fibre Channel spec, so there a sort of flaw in there, but with
little practical influence).

Now, in the ideal case the jitter is just gaussian phase noise. This case is so
simple that you can take the RMS value of the jitter and when multiplied with
the magical number of 14 and it is less than a cycle, you know that you have a
BER better than 10^-12. This means that once in a while (less than 1 bit out of
10^12 bits) the target D-flip-flop will sample the neighbor bit and not the
correct bit, since the gaussian noise have moved the phase more than half the
cycle. With low phase noise thats just very unlikely to happend.

In a similar way of thinking, if you dream of an exact deterministic behaviour,
you can just pure forget it. Get your design deepfrozen into 1 nK and you still
have non-determenistic, but the noise is ultra-low. Just face the music, you
have non-determenistic behavour all the time, you just have to learn to deal
with it and learn to reduce the bad effects of it.

DRAM memories in the computer I sit at is as such non-determenistic, not only
due to thermical noise and clock unstabilities, but effects like alpha-decay
occuring in the encapsulation material can discharge one or a few caps in the
DRAM. It just "feels" determinstic since most of the time it just works and
hey, we got the crappy software to thank for not experience the
non-determenistic behaviour of the actual computer.

So, OK... we just have to face the music then.

Well, what can we do to reduce the effects? Well, the BW limiting will have a
double effect in that it will help reducing (but not eliminate) higher
frequency noise. The BW limiting will also reduce the speed of changes.
Then, by reducing the time we look at the signal (a form of gating) we expose
ourself to less noise, but also, the voltage change possible during the time of
the blind eye is very small if the gate time is small. On the same time, we
must look long enought to avoid meta-stability in the logical gates, so we have
to balance those times.

That was what I was thinking about. Now, I'm sure you can invent all kinds of
ingenous devices to go around it, and people do. You can go on forever. It's a
endless story and among the major problems is to find the "optimum" balance
between complexity and relative determism.

Please go ahead and bore me to death on the issue.

This lack of determism is also what cause our classic oscillators to have
phase noise. It's there... just live with it.

Sigh....

Magnus - of to look for schematics...