[sdiy] VCO drift

[Karl Dalen]

In the Moog Rouge there is a buffer between  the current reference stage 
and the expo trannies! What's  the real reason to do this? I can  imagine
that 
the buffer could add inaccuracy because of the offset  voltage drift with
temp!
( 5mV/deg C) and shifting the frequency  of both VCOs and VCF! Is this
buffer
there just because the emitter of the reference cannot sinc the summed
currents 
and instead are sinc'ed by the LF353's output stage?  Or is this a Vebo
issue?
Or is it because the 10k current limiting resistor causes a offset that
makes this
type of design some what unstable?  Any clues!

VCO!

How temperature sensitive are the thresholds levels in a 4069, 
when used in oscillator designs in such as Renes CMOS VCO?
Especially when configurated as a comparator with gain ad it
goes hot?  (im not critiquing his design, they are nice.
(no its more of a general CMOS questioning/aspect,)

Also wouldn't a CMOS integrator also have quite high leakage
currents due to esd diodes and other things, e.g i could see a 
worst case leakage causing a drift of 5-30sec between cycles!
(depending on manufacturer, process etc.)
Perhaps not much to rant about but if a CMOS integrator VCOs
run parallel a zero drift oscillator that 10sec drift would be close 
to the edge of annoyingly fast phasing. At 5 sec drift i would call
the VCO defect!
 
Thanks!
KD

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