[sdiy] FPGA multiplier

[ASSI]

On Saturday 06 December 2003 21:34, Magnus Danielson wrote:
> 2) Avoid or reduce the amount of asynchronous flip-flops.

I think Magnus means the use of asynchronous Set or Reset, in which 
case I'd say you should avoid them like the plague. They are there 
because sometimes there is no other solution, but they are all too 
easily used for the wrong things.

Also in an FPGA, the number of clock nets is a constrained resource and 
while you can use any signal to clock an FF, you should really strive 
to just use the dedicated clocks. I your first design you should 
probably use just a single clock.

Both things are easy to mess up in VHDL and one should try a few very 
small examples to see when the logic synthesis will infer one or the 
other.

> [...] There often need
> for some asynchronous handling, like going between two synchronous
> clock domains (which is asynchronous to each other), but you want to
> make any such transition at as few places as possible.

Synchronization of completely unrelated clock domains is really not for 
beginners. You really need some expensive tools (clock generators with 
PRBS and arbitryry pattern output and controlled jitter). Only the PRBS 
part is easy to do in the FPGA itself, so you can do sort of a self 
test. Most commonly it is needed to implement UART or FIFO blocks - go 
find some free IP for that instead of re-inventing the wheel.

Another common pitfall is the use of clock gating. This really does not 
work in FPGA, instead you have to use clock enable/disable networks to 
"freeze" the FF in question while the clock is still running.

> Asynchronous
> designs is more difficult to do than synchronous design and testing
> is even more difficult.

I'd not tackle truly asynchronous designs with the free tools, I have 
enough gray hair already.

> 3) Use the flexibilities of the VHDL language to make the code
> readable rather than what makes "obviously minimal logic"

Seconded. Just like in programming, rule#1: Don't optimize. The logic 
synthesizer is normally much better at reducing combinatorial logic 
than any designer will ever be, especially as both the Altera and 
Xilinx FPGA are based on lookup-tables, where it ultimately does not 
matter if a function is made up of NOR or AND. Spend your time getting 
the relations between the combinatorial blocks correct, clear and 
concise. Also, avoiding tricky formulations will help to stay clear of 
any bugs in the synthesis engine.


Achim.
-- 
+<[Q+ * Matrix-12 * WAVE#46 * microQkb/Omega * XTk/30 * sonic heaven]>+

SD adaptations for KORG EX-800 and Poly-800MkII V0.8:
http://homepages.compuserve.de/Stromeko#KorgSDada