[sdiy] FPGA multiplier
jbv
jbv.silences at club-internet.fr
Sat Dec 6 17:50:19 CET 2003
This one if for FPGA gurus :
if I need to implement a 16 x 16 bits logic
multiplier with 32 parallel outputs and latched
i/o on Xilinx or Altera systems, what kind of
chip am I supposed to use ?
The question concerns actually the type of chip
(package, number of pins, size, PCB room) that
can be used. I'd like to compare with existing
multiplier chips...
Thanks,
JB
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