[sdiy] advice please -- aging chips and caps

Czech Martin Martin.Czech at micronas.com
Mon Aug 11 10:10:45 CEST 2003


Yes, an open is the likely failure. And you can often see am Al mushroom
coming out of the surface glas, well, the material must be somewhere,
so if it migrates away from some place it has to heap up soemwhere
else. Eventually a short may result also from this.

That's why we (like all other manufacturers) compute the absolute average
currents, obey the design rules and finally torture chips
in the oven for 1000 or more hours at worst case conditions.

I've seen only a few designs fail in that "life" test during
10 years (before the automatic current computation was invented).

Of course, this all relates to the design.
If you produce 1,000,000 ICs, you will find perhaps 300, or 200
100 or maybe only 50 which are tested good, but still fail
in the field. This depends on how much testing you want to spend
(testing is very expensive).
Most of them still look good in any test you throw them in, 
but they fail in the real application.

Some of them are not good, and some of those have open or short
metals, or contacts or vias. This is because process imperfections
can make wires shallower, or with some defect, or prevent
vias from filling with metal correctly, etc.

So, even if everything is done to make a robust design,
some chips will slip through that will fail in the field.

The older processes (I think 3u for CD4000) have broad metal
lines, and thick layers. But the vias and contacts were "hollow",
not filled with metal. These can be weak points.

The modern digital ICs with million of contacts and vias
have W filled "holes", but this doesn't semm to work
too good, so double vias are automatically placed to make
via defects unlikely.


m.c.

-----Original Message-----
From: Magnus Danielson [mailto:cfmd at swipnet.se]
Sent: Samstag, 9. August 2003 23:59
To: patchell at cox.net
Cc: synth-diy at dropmix.xs4all.nl
Subject: Re: [sdiy] advice please -- aging chips and caps


From: James Patchell <patchell at cox.net>
Subject: Re: [sdiy] advice please -- aging chips and caps
Date: Sat, 09 Aug 2003 14:30:24 -0700

> Personally, I wouldn't worry about the IC's.  Especially, the 4000 
> series.  By todays standards, the 4000 series is a very crude IC (large 
> features).  I have no idea what process is used to make them now, or even 
> then, but somehow I just don't seem to think of metal migration and 4000 
> series in the same thought (I could be wrong).
> 
>          My understanding of metal migration is that you need a high 
> current density flowing through the conductor (how high?? don't know) to 
> make this happen.  Since the 4000 series is both crude and low current, I 
> would put this at the bottom of things to worry about...
> 
>          I would be more inclined to worry about certain vendors parts (as 
> was discussed a couple of months ago)...

As I recall things, there was an issue about with metal migration early out in
semiconductor manufacturing. The trouble was too high current densities. As I
recall those problems was avoided by design rules which should still be in use
(in technology adapted from naturally).

What basically happends is that when the current density is to high (i.e. too
much amperes per square meter) the current is so strong it pulls the metal
atoms along for a ride. This will slowly thin out the point where current
density is strong (maybe from a small defect), which has the effect of reducing
the cross-section area and for the same current increase the current density
and thus accelerating the effect until failing catastrophically as a burnt
fuse.

Design rules helps to keep this not happening for times similar to that of when
the diffusions have migrated into each other sufficiently for the chip to fail
for that reason. This will also happend eventually. There is nice little tables
to look into for getting to know what is the probable lifetime of a certain
component, assuming it is correctly used.

I am sure our semiconductor-friends can shed more light over this...

Cheers,
Magnus




More information about the Synth-diy mailing list