[sdiy] Level Translation

[Scott Gravenhorst]

Ok, time for the list to give Scott another lesson in basic
electronics, but here goes:

home1.gte.net/res0658s/levtrans.gif

Is my idea (that I still have not tested), part of another
design.  My original need is to translate TTL levels to +/- 8
volts.

The way I think it _should_ work is this:

Supplies: +v = 10 volts, -v is -10 volts.

Since the input is expected to be the output of a CMOS gate,
I'm assuming it's valid levels to be 0 or 15 volts and not
much inbetween matters.

When the input is 0 volts, the input NPN is off and the it's
collector should be at or near 10 volts.  This should cause
the PNP to turn on which should in turn cause the output NPN
to turn on.  The output NPN's collector should then be at or
near -v or -10 volts.

When the input is 15 volts, the input NPN is turned on and
it's collector should be close to ground.  This should cause
the PNP to be off, which will then not supply base current to
the output NPN, turning if off.  This allows the output NPN's
collector to rise to near +v causing a +10 volt output.


Ok, I'm here to learn, so tear me apart.

If this solution is totally noob, so be it, but I am also
interested in a solution to this.  (I'd rather not use op-amps).
 

Tim Ressel <madhun2001 at yahoo.com> wrote:
>Yo, Can you spare a cup of neurons? I'm all out...
>
>This is something I've never been good at: I have a
>cmos gate putting out a 0-15V signal, and I need to
>translate that to +/-10V. I just can't seem to wrap my
>move-addled brain around this today.
>
>TIA
>
>--TR
>
>
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