[sdiy] Finding the correct IC...

media.nai at rcn.com media.nai at rcn.com
Thu Jun 20 19:55:31 CEST 2002

At 9:43 PM +0100 06/19/02, Neil Johnson wrote:
>> >D is for "Data"
>> Not according to the logic textbook I have.
>I just checked in mine:
>Logic Designer's Manual, John D. Lenk, 1977
>  "D-type flip-flop ... requires only one data input in addition to the
>clock input" ...and the schematic diagram is courtesy of Honeywell.

Where does that say "D" stands for "data"??  Besides, "data" isn't much of
a distinction among flip-flops.  It's all data if it stands for something :)

"Another flip-flop available in an integrated circuit form is the clocked D
(delay) flip-flop..."
_Fundamentals of Logic Design_, Charles H. Roth, Jr (1975, 1992).

The same book also lists it as "Delay" in a table entitled "Determination
of Flip Flop Input Equations..."

>> That's a type D with SR.  I was referring to a plain SR (made with two
>> NOR gates).
>Again, from Lenk, if both inputs are set high, both outputs go low.

Then Q and Q' would be the same.  Since they are supposed to be
compliments, R = S = 1 is "not allowed".

>If both high levels are then removed from the input simultaneously (which
>never happens in practice because this is an analogue world :) the state
>of the output cannot be predicted.  Harry's spot on there.

Right, if both inputs are changed to 0 at the same time it might oscillate,
or have other unpredictable results.  Compared to modern digital the gate
delays of these older logic families are quite large, so "simultaneously"
seems possible depending on what is driving it.

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