[sdiy] Finding the correct IC...

media.nai at rcn.com media.nai at rcn.com
Wed Jun 19 21:54:48 CEST 2002


>>SR and D are two different types, although there are type D (delay)
>>flip-flops with set-reset capability.
>
>D is for "Data"

Not according to the logic textbook I have.

>>According to the rules (although Harry might have his own ideas :) you are
>>not supposed to connect both S and R to the same value at the same time.
>
>Arrgh what's 'Harry' got to do with this one ???   ;^P
>
>BTW you can (on a 4013 with positive set and reset)

That's a type D with SR.  I was referring to a plain SR (made with two NOR
gates).

>hold both
>S and R low... or move either one to high...
>
>Both high is the "disallowed" state... it will make Q and Qnot
>high at the same time.  When you release them... its a race...
>the last one "high" wins.

Right.

>But it does not HURT anything to use the disallowed state... and
>I often do if I want to force both Q and Qnot high.

See, I knew you would have something to say :)

>Maybe it should be called a "disliked" state ???

I thought that was New Jersey ;)

>(and so should a BBD...)
>
>H^) harry





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