[sdiy] super cheap synthisizers

phillip m gallo philgallo at attglobal.net
Wed Jun 12 21:16:41 CEST 2002


"With a phase accu the output is frequency is independent from the sample
frequency".

--->Yes, sample rate is constant the "phase increment" is variable.
Although if this is a single proc/DCO your sample rate can adjust slightly
to allow for integer multiples of Frequency Increment. This sampling rate
variation does not have to violate your output filter requirements.

"This way the frequency is rock solid but you wave form does NOT always
start
with sample #1."

--->Your phase accumulator can be loaded to begin at any point along the
wave from start to finish.

"Note that there will be amplitude jitter when doing a saw wave this way."

--->No amplitude variation should be expected using just the phase accum's
raw (saw) count directly as a waveform.

"A high sample rate like Paul uses solves this problem".

---> For DCO's i recommend 48-50K depending on how "binary" your algorithm
is.

The phase accu method is only good if you use a DAC.

---> The phase accum doesn't require a DAC to generate stable amplitude
Sawtooth waveforms.

"but because the generated wave forms are always full code, you don't need a
high resolution DAC.
Think 8 bit R2R will be plenty.

--->The DAC resolution will drive a noise source which is the noise
resulting from "quantization error".  This error is the result of the
staircased waveform that emits from the process. Filtering can fix this but
is best implemented in an "adaptive" way. This is a "rub" similar to the
"integrator reset" amplitude issue. Now this is for a synth so "one man's
meat is anothers poisen" (cliche' targeting vegan's i guess). IMHO a 12 bit
DAC is a good compromise between resolution and low cost.  I use 16.

Using a phase accu to reset a ramp like some pp proposed won't work.
This would cause frequency jitter AND give low frequency resolution.
Unlike the sample read out, the ramp has no fixed phase relation with the
accu. Frequency jitter because the number of clocks in-between resets will
differ.
Low resolution because this would be the same as using a "slow" timer.

---> Your frequency jitter occurs mainly as a result of the freq. of  your
sample rate, the sophistication of your rounding technique, and the
determinism of your algorithm.  Again and single DCO/uP solution can pull
all kind of non-exotic tricks to minimize jitter.

regards,
p


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