[sdiy] super cheap synthisizers

jbv jbv.silences at club-internet.fr
Wed Jun 12 10:34:18 CEST 2002




> No the AVR won't do.
> I think a timer speed of 4Mhz is about the minimum for good results.
> Even at 16 Mhz, a 1 Mhz timer interrupt means there are
> only 16 clock cycles between two interrupts.
> Because we need some jumps and jumps take more time,
> in practice this translates to about 10 instructions.
> This is barely enough for jumping to the interrupt handler and updating
> and evaluating two 16 bit "soft timers" and setting the output bit.
> Let alone evaluating midi or do a envelope or two.

(snip)

> Maybe adding a external timer IC like the 8254 is a solution.
> That would be 3 independent 16bit counters, enough for 3 DCOs
> leaving an other 3 timers inside the AVR free for generating CVs.
> But this is no longer a "single" IC solution.

Forget about timers.
Here's the trick I used for some experiments that might become
some day a DCO : run your uC at a clock rate that is a multiple
rate of your sampling rate. Then divide the clock rate and use
that signal as interrupt.
The SX is a good candidate for this : some units can run at 50 Mhz
(or even more but I haven't tested such clock rates as 75 or 100 MHz).
So using 48 MHz as clock rate, with a simple :1000 divider used as
interrupt gives you 1000 clock cycles to play with...

Yes I know, it's not a "1 chip solution". But if you're planning
to put several uCs in parallel, then you can have 1 single circuit
for clock generation & division, and use those same clock & interrupt
signals for all uCs in parallel.

The kind of DCO I've tested implements the Matthews algo, a phase
acc osc like in Music V. But such a phase acc is not much without
linear interpolation, and to achieve that you need multiply, and almost
no uC offers that, only DSP.

So the idea I had was to add an external multiply such as an FPGA.
Actually, I've been trying to figure out the best ratio between simplicity
and power of such an architecture, and found that a uC (such as SX) +
multiply + SRAM as core unit (several can be put in parallel), plus
clock / interrupt generation + ADC / DAC shared by all units is a very
attractive & promising architecture to run all kind of algos : multiple
DCOs of course, but also granular osc & reverbs, waveshapers...

But then I had to put it back on the shelf because of lack of time
(I've heard that song before)...
Anyway, may be some ppl remember this project being discussed
here before (at least the archives might remember)...

JB






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