[sdiy] super cheap synthisizers

[mikko.a.helin at nokia.com]

Hello,

I have another way in mind which could be used with AVR's. I don't like to use  timers or interrupts, instead I would select a clock rate that is multiply of MIDI rate. At 31250 kbit/s you will receive 3125 bytes/sec max., so with 8MHz crystal you'll have 2560 clock cycles/instruction to play with. You propably want to update the phase accumulation registers more often than that, so the 2560 clocks/instruction cycles could be divided into 10 slots of 256 instructions each. That means that the frequency can be modulated at 31250 Hz rate (not enough, why?). The most signifigant bit of phase acc reg is the output to some port/pin of the uC, and it can be used as a square wave and/or converted to pulse to discharge the cap in sawtooth generator. Also to generated one or two octave below wave didive the frequency just by two or four (you don't need own phase acc reg for it, just a counter reg which can be a byte).

In the beginning of every slot the phase acc reg is incremented (or decremented, including the portamento stuff) and the most signifigant bit output (for each osc). In the first slot also the UART/MIDI port is read and the MIDI stuff interpreted (if there's no data then put a value to a count register which is used to loop a NOP loop to fill the 256 instruction cycle with something). In the other slots the lfo's, eg's etc. are updated and the data is sent to (multiplexed) DAC. The lfo's and eg's can obviously be update more than once. It could be maybe better if the number of slots is a factor of two (8 or 16, 320 or 160 cycles/slot).

So the skeleton code could look like this (actual code must be codec with assembler):

while(1)
{
	// slot 1
	update_phase_accumulators();
	time_to_waste = read_and_interpret_midi();
	do_nothing(time_to_waste);

	// slot 2
	update_phase_accumulators();
	generate_env_vcf();
	generate_lfo_vcf();

	// slot 3
	update_phase_accumulators();
	generate_env_vca();
	generate_lfo_vca();

	// etc.

	// slot 16
	update_phase_accumulators();
	do_nothing(TIME_TO_WASTE_FOR_SLOT_10);
}

-Mikko

> -----Original Message-----
> From: ext jbv [mailto:jbv.silences at club-internet.fr]
> Sent: 12. June 2002 11:34
> To: synth-diy at dropmix.xs4all.nl
> Subject: Re: [sdiy] super cheap synthisizers
> 
> 
> 
> 
> 
> > No the AVR won't do.
> > I think a timer speed of 4Mhz is about the minimum for good results.
> > Even at 16 Mhz, a 1 Mhz timer interrupt means there are
> > only 16 clock cycles between two interrupts.
> > Because we need some jumps and jumps take more time,
> > in practice this translates to about 10 instructions.
> > This is barely enough for jumping to the interrupt handler 
> and updating
> > and evaluating two 16 bit "soft timers" and setting the output bit.
> > Let alone evaluating midi or do a envelope or two.
> 
> (snip)
> 
> > Maybe adding a external timer IC like the 8254 is a solution.
> > That would be 3 independent 16bit counters, enough for 3 DCOs
> > leaving an other 3 timers inside the AVR free for generating CVs.
> > But this is no longer a "single" IC solution.
> 
> Forget about timers.
> Here's the trick I used for some experiments that might become
> some day a DCO : run your uC at a clock rate that is a multiple
> rate of your sampling rate. Then divide the clock rate and use
> that signal as interrupt.
> The SX is a good candidate for this : some units can run at 50 Mhz
> (or even more but I haven't tested such clock rates as 75 or 100 MHz).
> So using 48 MHz as clock rate, with a simple :1000 divider used as
> interrupt gives you 1000 clock cycles to play with...
> 
> Yes I know, it's not a "1 chip solution". But if you're planning
> to put several uCs in parallel, then you can have 1 single circuit
> for clock generation & division, and use those same clock & interrupt
> signals for all uCs in parallel.
> 
> The kind of DCO I've tested implements the Matthews algo, a phase
> acc osc like in Music V. But such a phase acc is not much without
> linear interpolation, and to achieve that you need multiply, 
> and almost
> no uC offers that, only DSP.
> 
> So the idea I had was to add an external multiply such as an FPGA.
> Actually, I've been trying to figure out the best ratio 
> between simplicity
> and power of such an architecture, and found that a uC (such as SX) +
> multiply + SRAM as core unit (several can be put in parallel), plus
> clock / interrupt generation + ADC / DAC shared by all units is a very
> attractive & promising architecture to run all kind of algos 
> : multiple
> DCOs of course, but also granular osc & reverbs, waveshapers...
> 
> But then I had to put it back on the shelf because of lack of time
> (I've heard that song before)...
> Anyway, may be some ppl remember this project being discussed
> here before (at least the archives might remember)...
> 
> JB
> 
> 
> 
>