[sdiy] Biphase Mark (OT)
Magnus Danielson
cfmd at swipnet.se
Sat Jul 20 23:02:21 CEST 2002
From: "Alex Stettler" <alex at xatomic.ch>
Subject: [sdiy] Biphase Mark (OT)
Date: Fri, 19 Jul 2002 23:51:55 +0200
> Hi all,
Hi Alex,
> I designing a little circuit, which converts 2 analog audio channels to a
> SPDIF-output.
> I need this circuit board for testing different AD-converters for a new
> project.
> As some of you probably now, the SPDIF signal is biphase mark encoded. So my
> question is, does anyone of you know a simple circuit (preferably with
> standard logic ICs) to convert a given clock signal and the serial SPDIF
> datastream into the needed biphase mark format?
Well, for the basic bi-phase encoding you need two D-flipflops and two XOR
gates. Both DFFs clocked from the same clock (bit-clock), one samples the
input data, one samples the outgoing bit. One XOR gate combines the outputs
of the DFFs and one XOR gate takes this signal and XORs with the clock.
Now, that is simple enought.
This satisfy this table (columns for previous state, rows for transmitted bit):
0 1
0 11 00
1 10 01
What is not as simple is to generate the preamble codes, since those builds
on code-violations to the above scheme.
The preamble codes are:
0 1
Z 11101000 00010111
X 11100010 00011101
Y 11100100 00011011
If we revert the preambles through the normal encoding we get:
Z 0A1B
X 0AB1
Y 0AA0
but only after adding this little addition to the encoding table:
0 1
0 11 00
1 10 01
A 01 10
B 00 11
So, one must alter the machinery to handle these deviations in order to
properly encode the preambles. Also, this have to be coordinated with the
data such that correct preamble is sent for L/R samples. Also, one really
should ensure that the Z-preamble is sent instead of the X preamble, every
192nd frame even if no valid sub-data is sent.
If we now generate a signal C (for Codeviolation) whenever we have either A or
B and let this signal invert the output (i.e. we toss in another XOR gate)
and let A generate a 1 and B generate a 0, then the encoding becomes:
D C
Z 0110 0101
X 0101 0110
Y 0110 0110
Now, these are striking similar, but further work I let as an exercise to
the reader (hints: use another XOR and figure out when to flip it and you
should force C to 0 non-preamble part of the signal).
The real reason I leave it open in this end is that it is actually difficult
to figure out exactly which signals you have and what timings they have. The
basic encoding scheme should be apparent anyway. So, we've spent a pair of
DFFs ('74) and a handfull of XOR gates ('86). Toss in what you need.
Cheers,
Magnus
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