[sdiy] FPGA digital audio

[patchell]

harry wrote:

> Since it was my first design, I had the luxury of an experienced engineer, who
> looked at my design and assured me the smallest available FPGA was more
> than big enough.
>
> I learned the syncronous design the hard way... after having the design fail to
> work as suggested in the simulation.  I also found that straight decoding using
> and gates (etc) worked very well. In the "real world" you would never do it that
> way... for the board space you'd burn up.

    Actually, it is amazing how in the gate array, things you would do with IC's to
save board space actually use up more gate array realestate.  After I had completed
my first design, and got it working, I read some document that Xilinx had on how the
router worked with the gate array and it had lots of suggestions on how to save
space.  After following the suggestions from the Xilinx literature, I was amazed
that I gained about 5% or so.  Sometimes, what looks redundent on the schematic end
up using fewer resources.

>
>
> I'm still thinking PAL or GAL or SPLD... a Spartan II might be a little overkill
> for a LED driver... OTOH I could probably do the entire quantizer with it....
>
> H^) harry
>
> Magnus Danielson wrote:
>
> > From: harry <harrybissell at prodigy.net>
> > Subject: Re: [sdiy] FPGA digital audio
> > Date: Sat, 05 Jan 2002 12:57:43 -0500
> >
> > Harry,
> >
> > > Hmmm... with the price of the chips I'd go with a bigger one and let
> > > the router do it. Like PCBs... there is no doubt that a careful hand design
> > > would outperform it. Computers are persistant, but not clever.
> > >
> > > Another rule is don't fill the chip. I started at 65% with the initial
> > > design and
> > > went to 70%... now that it works.
> >
> > There is a golden rule with FPGA design:
> >
> > It is easier to scale down later (when you know how much you really
> > needed) than trying to scale up (since you did not have enougth space
> > left).
> >
> > The trick is to choose encapsulation and pinassignments with scaling
> > up/down issues in mind. Expensive experience have told us that if you
> > choose a too small package ("It MUST fit") to grow in, then one has to
> > redo the PCB just in order to get a larger FPGA. If you choose with a
> > bit of margin, you may later chose a smaller FPGA in the same capsule
> > but with smaller amount of CLBs (and less price).
> >
> > The danger is naturally the classical Creeping Featurisms and bad
> > designs (taking less care of silicon usage). What you however attempts
> > to counter-balance is lack of early design complexity analysis and
> > lack of actual problem for which the design must solve.
> >
> > Experince has shown that not too selldom has the initial views on how
> > large a design becomes been too optimistic and that the full scale
> > view of what the actual problems to be solved where much more than
> > originally perceived.
> >
> > Cheers,
> > Magnus
>
> --
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--
 -Jim
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