[sdiy] Top octave CPLDs

[Magnus Danielson]

From: Tim Ressel <madhun2001 at yahoo.com>
Subject: [sdiy] Top octave CPLDs
Date: Mon, 23 Dec 2002 13:18:51 -0800 (PST)

> Yo,

Jo Tim!

> Well, almost working. After chasing a nasty problem
> for a while I discovered that the asyncronous reset I
> am using is causing the problem. It appears internal
> delays in the CPLD are inconsistant. I got lazy and
> assumed the delays would pile up as the schematic
> suggests. This does not appear to be the case. 

Which gives you a good hint on why asynchronous resets is deprechiated
in most modern designs. Actually, most of the time you are better of not
knowing there are things like asynchronous resets and latches. Designing
digital stuff in the fast lane forces you to loose some options you once
thought you had... and the reasons for it is good once you realized what
life is inside a chip rather than what we've used to out on the PCB.

Once you tripp over the egde of a chip things just take
ffffoooorrrreeeeevvvveeerrrr! Just getting through the output buffer
takes time.

> To make a long story short, I have to re-draw the
> whole darn thing with syncronous resets. 
> 
> But is does mostly work. It was nice to hear the tones
> coming out.

It is pleasing to get to that point, isn't it?

Cheers,
Magnus