[sdiy] midi clock

[patchell]

    Beleive it or not, I do that all the time.  The Xilinx Field
Applications Engineer was amazed when he saw the designs I did without
simulation.  When the place I worked for originally started doing the
FPGAs, we could not afford the simulator (it was an extra $4000 on top
of the $10000 for the compiler....the software is much cheaper now...ie
FREE).  I got used to doing it blind...and for the most part, it was
pretty easy to get the designs to work the first time, or at least
nearly so.

Tim Ressel wrote:

> Yo,
>
> --- patchell <patchell at silcom.com> wrote:
> > (Logic simulators are for Wimps and
> > Bedwetters, but it does save time)
>
> Well, now. Try doing a 10,000 gate FPGA design without
> using a simulator  8-0
>
> --tr
>
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--
 -Jim
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