[sdiy] Slightly OT, Logic Analyzers...

Magnus Danielson cfmd at swipnet.se
Mon Aug 5 23:01:46 CEST 2002

From: The Proteus <proteus at ugwarehouse.org>
Subject: [sdiy] Slightly OT, Logic Analyzers...
Date: Mon, 5 Aug 2002 01:44:23 -0700 (PDT)

> All,


> 	I've been contemplating designing a very small logic analyzer with
> some Linux software to run it.

Oh, you too...

> One of the features I'd like to have is support for multiple logic types
> (TTL, CMOS, LVTTL, etc...). Now, from what I'd assume, the logic capture
> hardware is basically a latch being driven at high frequencies, and then
> that latch data is being stored in a buffer memory somewhere.

Well, yes... but no... 

Not actually a latch, but a D Flip-Flop.

> That's all simple to me... the question I'm kicking around currently is how
> to get the input voltages in line with the latch. If you've got a 5V latch
> and the input is a LVTTL signal, how do you translate the high, low, and
> threshold voltages appropriately? This isn't a big deal for basic TTL<->LVTTL
> or CMOS<->TTL type circuitry, but when you get down to 1.8V and 1.5V Vcc
> rails, the appropriate level translator could get quite tricky to design -
> especially in commercial logic analyzers where there are 128+ channels. 
> 	Does anyone have any ideas on a good, low-cost level shifter I
> just described? Yes, my goals are lofty to top out at commercial analyzer
> channel counts, but hey... let a young kid have his dream. ;-)

Well, what you basically want to see is a comparator, isn't it?

You have a fast comparator for each input, with the output driving suitable
DFF hardware. You have the second input of the comparator wired up to some
suitable reference voltage. For a pod you probably wire all to the same
voltage reference and then drive it from a suitable DA. How else should it

Naturally, there is many ways to slice and dice the cat, but in the end this
is basically what happends.

Naturally, you want to have means to trigger, both by pattern and by state,
you want to be able to supply a clock and you probably also want to be able to
handle pretrigger data.

The core should fit nicely into a FPGA, toss some memory on the side if the
internal memory isn't enought (it isn't).

No, I haven't been thinking about this before... ;O)


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