[sdiy] Slightly OT, Logic Analyzers...

The Proteus proteus at ugwarehouse.org
Mon Aug 5 10:44:23 CEST 2002


All,

	I've been contemplating designing a very small logic analyzer with
some Linux software to run it. One of the features I'd like to have is
support for multiple logic types (TTL, CMOS, LVTTL, etc...). Now, from
what I'd assume, the logic capture hardware is basically a latch being
driven at high frequencies, and then that latch data is being stored in a
buffer memory somewhere. That's all simple to me... the question I'm
kicking around currently is how to get the input voltages in line with the
latch. If you've got a 5V latch and the input is a LVTTL signal, how do
you translate the high, low, and threshold voltages appropriately? This
isn't a big deal for basic TTL<->LVTTL or CMOS<->TTL type circuitry, but
when you get down to 1.8V and 1.5V Vcc rails, the appropriate level
translator could get quite tricky to design - especially in commercial
logic analyzers where there are 128+ channels. 
	Does anyone have any ideas on a good, low-cost level shifter I
just described? Yes, my goals are lofty to top out at commercial analyzer
channel counts, but hey... let a young kid have his dream. ;-)

Regards,

Prot

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