[sdiy] Speaking of CMOS....

[mark verbos]

run the signal through a 12k resistor then put a clamping diode to to 
the +8 volt power rail cathode (neg side) to the rail, anode (pos. side) 
to the signal. That will limit the signal to that power rail.

or

run the signal through a resistor devider something like a through a 15k 
with a 47k to ground should work.

mark



Peter Grenader wrote:

>I'm working with a 4053 that specs a 15 p-p volt max for analog information
>going through it.  It seems a pair of 8 voltge regulators did the trick. One
>of the signals going into it however will be from CMOS and is a 11 high
>static state logic enable signal.
>
>Would it be wise for me to  pop a PNP in there instead to keep the 11 volts
>the hell away form the 4052, given thats 3 volts higher than it's Vdd?
>
>I'm thinbking yes, but wanted some guidedance from the masters here.
>\thanks in advance,
>
>Peter
>
>
>