[sdiy] Trigger delay schematics

Sowa Roman Roman.Sowa at upc.com.pl
Wed Apr 10 16:04:54 CEST 2002


No! Don't use b***t brigade, or some very nice guy on this list will bite
you bad. ;)

I'll try to describe it without  schematic:
NPN transistor with 100k resistor at base, 100k log (audio) pot in series
with 1k
resistor between collector and power supply rail, emmiter to ground. Also -
22uF
cap between collector and ground. A comparator (made of opamp or CMOS
non-inverting gate) is connected to collector too. Output of comparator
follow
by CR network to form the second trigger (22nF capacitor in series, then 10k
resistor to ground). Input of this circuit is at this 100k resistor going to
NPN.
On the other side you should get delayed triggers with delay time variable
from
few (20?) miliseconds to about a second.

This is very simplified circuit, I just made that up. Never tested, but it
must work
I hope :)

Roman

""-----Original Message-----
""From: Peter Cooke [mailto:p_cooke52 at hotmail.com]
""Sent: Wednesday, April 10, 2002 3:08 PM
""To: synth-diy at dropmix.xs4all.nl
""Subject: [sdiy] Trigger delay schematics
""
""
""
""Hi,
""
""Does anyone know of any schematics for a trigger delay 
""circuit?  This would 
""be used where a trigger signal would be used to drive two 
""separate VCA 
""envelope generators with one sligtly later than the other to 
""create a sort 
""of echo effect.  Ideally, the delay would be variable.
""
""Could one of the bucket-brigade digital delay chips be used?
""
""Thanks very much,
""
""Peter
""
""
""_________________________________________________________________
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