AW: [sdiy] [OT] puzzling EPROM problem

[Czech Martin]

EPROMS are basically analog circuits, that is inside.
A floating (poly) gate capsuled in oxide or nitride is charged via
programming.
This changes the threshold level of the mosfet underneath.
If you now select the secondary gate of the mosfet (wordline)
and the circuit selects the right bitline, this particular mosfet
will pull more or less current to GND out of the bitline,
depending on the captured charge in the floating gate
and also aging of the mosfet underneath.

A read amplifier will notice the voltage drop on the bitline
and decide "1" or "0", according to it's own threshold level.

According to the quality of writing the level of "0" and 
"1" is variable, a bad level may lead to much longer
comparator decision time (can you say meta stability?), 
a very bad level to a constantly
wrong reading.


The big question with such devices is allways: retention.

How long will the information stick in the EPROM,
especially at elevated temperatures?

Since you and the programmer can not see the analog bitline level,
it is difficult to detect a bad logic level.
Therefore programmers write over and over to make it more
probable that all bits are really good level.

FLASH, EPROM and EEPROM devices are a bit flimsy
in this sense, and I sometimes really wonder that
these memories work that good.

It's the same with mask ROM, therefore our older
ROM devices had a "margin test" feature, the
read amp could be switched to a more critical level,
if the ROM still worked you knew that there is
still a good margin to the real threshold.

Anyway, I assume that your EPROM in question worked
perhaps perfectly well in the checking device,
because the timing was marginal different.
It did not work in the machine, because the timeing was more
critical. We should consider that higher supply noise
in the machine will make memories slower anyway.

m.c.