[sdiy] VC ADSR

[patchell]

Paul Maddox wrote:

> Dear all,
>
>  Im thinking of haveing a go at a VCADSR module...
>
>  Couple of questions..
>
> I know that the attack phase of most Capacitor based ADSR is not liked by
> many..
> should I try and get a linear attack stage, then log Decay/release?
>
>   Should I include an option for Lin/Log?
> ie,
>
> Lin ;- Linear Attack, Decay AND release
> Log;- Linear attack, log decay and log release
>

    Now, this is not something I had never thought of before, being able to
change from Linear to Log depending on which step you are in....I will have to
think about this a bit.

    Also, the way I go from Linear to Log (a continuous transistion), is that I
use a CA3280 for the OTA in the timing circuit.  I use Iabc to control the time
constant, and I use Id to control if it is linear or log.  It is a little
difficult to say in a few words how this works.  But, I am quite satisfied with
the way it does.  Schematics are on my web site under "Synth Modules".

>
>   Also what about trigger/retrigger/gate?
>

    Oh, yes, and it is not all that difficult to do.

>
>  Should I have an option to allow retriggering (ie reset whole EG the moment
> the garte rises)
> or should I use seperate trig/gate lines?

    I prefer seperate trig/gate....

>
>
>   Paul Maddox
> _______________________________________
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--
 -Jim
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