[sdiy] Re: current mirrors

[Magnus Danielson]

From: jhaible at t-online.de (jh.)
Subject: Re: current mirrors
Date: Thu, 8 Nov 2001 02:23:06 +0100

> > if we assume matched transistors, we can assume
> 
> > I   = I
> >  B1    B2
> 
> Well, the point of this all was the effect of transistor mismatch.
> If Vbe1 = Vbe2, but the transistors are different, Ib1 != Ib2.

Indeed, that just helps on further... but even if they are a perfect
match, you have a flaw, that of the curcuit itself. I just wanted to
show the relations to start with.

> > You can then vary this theme further. All this was naturally done with
> > a very simple model, but it is sufficient to show the general behaivour.
> 
> Yes, what you show is the remaining error as a function of beta
> even for perfectly matched transistors.

Exactly. Now, toss in more imperfections as you like. I'd go for the
3-transistor current mirror to start with at least.

Another possibility is the 4-transistor cascoded mirror etc. etc.

Then we have the issues of temperature matching etc. etc.

The question is just how perfect a current mirror do we need.

BTW, the SSM 2044 patent teaches you a few bits on current mirrors,
which is needed for most of that chip is just current mirrors!
Current mirror galore!

I don't know how the SSM 2018 is built up thought. Any pointers?

Cheers,
Magnus