[sdiy] sync'ing BBD delays

[jh.]

Hi Don,

> This appears be in the class of phase locked loop applications where
> you really don't care about the phase.  The PLL works hard to keep the
> phase accurate, not the frequency, but for a BBD clock we only care
> about the frequency.

Yes, but we want the frequency without error.
As we allow for a static phase error, we get the desired error-free
frequency.

> The worst case situation would be if the VCO
> frequency was correct but the divided-down phase happened to be wrong,
> the PLL would radically tweak the frequency until the phase came into
> alignment.

Right - I didn't think about that.

> So I think that resetting the divide-by-N counter on each sync
> clock would improve things greatly.

Would this be similar to a Phase locked loop with additional f control
to "kick start" ?


>    (1) include a CV adder to set a (manual) starting value.
>    (2) use the lower leg of the filter (where the cap normally
>        is grounded) to bring in the LFO that slightly modulates
>        th edelay time (common practise in BBD echoes.)
>
>    Maybe (1) could alternatively be done with a very small min / max
>    frequency rate (two resistors on 4046). The idea is to set the
>    delay time approximately by hand, and then let the PLL only do
>    slight corrections (to avoid long adjustment times).
>
> These are physically the same thing, right?  They both directly set
> the frequency of the VCO without waiting for the loop.

I think it's different, but I'm not sure which one would be better.
(1) doesn't limit the range, just gives a starting value for f.

The the 2-resistor method, OTOH, actually limits the VCO range and
forces the PLL to either lock within this range, or not lock at all.
With a PD that allows locking on harmonics, that could be quite interesting:
The echo time would not be tracking the clock anymore, but it would
be hard sync'ed or "quantized". (Maybe).

JH.