[sdiy] PAL/PLD

[Neil Johnson]

> ... does anyone know why it is that PLDs have such high initial
> (frequency independent) current consumption ... ?

Sense amps, lot of them.  Fast switching means small signal swing (takes
less time to shuffle the charge back and forth) but for good noise
immunity you need high-gain amps = high current consumption.  And, as you
said, the connection matrix has LOTS of wires, each needing a sense amp.

I think in one PAL/CPLD/FPGA series it turned off the sense amps if
nothing was changing, then turned them back on when I/O pins started
changing again.  Managed to get the current consumption down quite a bit.

Alternatively, have a look at the old Philips XPLA series, later bought by
Xilinx - see the Xilinx website
(http://www.xilinx.com/partinfo/databook.htm#cool) in the CPLD section for
the XPLA3 series.  For example, the XPLA3064XL is almost linear from 0 to
25mA over DC to 140MHz frequency range for a design with four 16-bit
counters.  They don't use sense amps at all, but some funny little
"cascaded chain of pure CMOS gates" which gets them down to a static
current of 100uA.

'Digital' is 'analogue' spelt wrong.

Neil
--
Neil Johnson :: Computer Laboratory :: University of Cambridge ::
  http://www.cl.cam.ac.uk/~nej22           +44 (0) 1223 334 477