[sdiy] PAL/PLD
Emmanuel AMADIO
emmanuel at postimpressions.co.uk
Tue Feb 27 12:21:57 CET 2001
sHOULDN'T BE TO HARD TO DO WITH A PLD, A SMALL FPGA MIGHT BE BETTER, 32 MHZ IS NOT A PROBLEM.
PROBLEMS ARE LAYOUT, DECOUPLING AND PROGRAMMING THE DEVICE....
DOING THAT WITH SCHEMATICS IS NOT HARD OR YOU COULD USE VHDL WHICH IS PRETY NEAT FOR THAT JOB AS WELL.
Paul Maddox wrote:
>
> Dear all,
>
> Is there anyone on here who's good with PAL/GAL/PLDs?
> and if so do they fancy a challenge?
>
> Id like to find this;-
>
> 8Bit full adder with carry in+Carry out+Latch for output and Output
> Enable...
>
> so I can add two 8bit numbers, with carry, latch the output the enable the
> output of the latchs to store it.
>
> Oh BTW, I also need them to be FAST I mean 32Mhz+
> I could do it useing some discrete logic, but this would save me about 60%
> of the chips I need..
> Id need at least 4 initially, probably more...
>
> Paul Maddox
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