[sdiy] LFO, analog computers

[Martin Czech]

:::> other. Will normal speakers/headphones output such low frequencies? What 
about a
:::> soundcard? Most give a range of 20-20kHz, but shouldn't lower frequencies 
come
:::> out fine, or amybe distorted?

Headphones: serious fall of of response arround 30Hz-20Hz usually.
Speakers: Anything you can carry allone will drop of @ 50Hz,
radiation resistance of a speaker cone gets simply imaginary there,
so not much power output, but lots of heating and membrane
displacement. There was once a 80cm Woofer by Fostex, but even that
won't do. A horn speaker for such low frequencys is incredible
large. Perhaps piston?

Ears: large displacement, you hear nothing but distortion: DANGEROUS!

:::>
:::> 2) Can capacitors be made by doping silicon, as chips are? I'm thinking, if 
they
:::> can be, a whole lot of sample and holds might be possible to make a sort of 
an
:::> analog hardrive; think : one capacitor the equivalent 32(64...) bits of 
data.

There are severall ways to have on chip capacitors:

MOSFET like: highest capacitance/area due to very thin dielectric
(SiO2 oxide <100nm), but very nonlinear, you need some inversion to have
reasonable capacitance at all. You can't go rail to rail. May be better
if depletion type mosfets are available. Danger of oxide breakdown.


Junction: Capacitance depends on voltage, the more abrupt the doping profile,
the more capacitance, but also the lower the junction breakdown.
Always some leakage, especially at higher temperature.

Dual-Poly: Gate poly silicon and oxide and capacitance polysilicon
sandwitch capacitance, sometimes combine with metal-oxide-metal
sandwitch. The oxide is not as thin as gate oxide, thus less 
capacitance/area. Sometimes nasty effects like matching problems,
nonlinearity.

Metal-Metal: the usuall choice in CMOS processes <0.25 um.
Very linear, almost ideal, but lower capacitance/area then mos.

All these capacitances are planar. DRAM uses deep holes or trenches
in order to have a vertical capacitance, obviously to save area.
The means very special process which doesn't match very good with
logic process needs. 

However, all these capacitances consume large areas. You can estimate
that a 6" 0.5um tech wafer with simple logic process will cost 800 USD.
A 8" wafer with 0.25u tech may cost 1700 USD. This means: chip area is
expensive, so you try to avoid capacitors by all means.
Sometimes you can't avoid: "compensation", or internal supply bypassing caps
for logic chips (bond wire inductance does not allow currents with high
frequency enter the chip, so without internal capacitance you observe
severe voltage drops @ the clock edges).

All these capacitances are more or less leaky, but even if you use
the allmost ideal mosfet or metal cap, you still need a junction (FET)
to charge or read it. Thus junction leakage and the need for refresh.


The basic idea of "analog" multilevel storage of digital data is still
there, but different. Instead of charging a cap you shoot electrons
into oxide. EEPROM or FLASH technology. The SAN corporation proposed
256 level storage in 1996 for their FLASH and predicted the end of hard
disk drives...

Never heard what the final result was.

sorry for beeing academic.

m.c.