[sdiy] CMOS schmitt trigger question
music.maker at gte.net
Thu Dec 27 10:42:47 CET 2001
media at mail1.nai.net wrote:
>At 3:46 PM -0500 12/22/01, harry wrote:
>>> I thought only the inputs needed to be terminated.
>>That's right. Don't tie the outputs...
True, and to tie an input is different from termination.
Tying an input high or low just prevents that gate from
doing a linear amplifier thing that will cause the
two output transistors to be in some resistive state
between full on and full off. This will cause the
device to waste power by unnecessarily drawing current
from Vdd to Vss thru both output transistors. When the
gate is driving a true high or low, one of the output
transistors is full off and prevents any significant
current draw through the pair while it remains in that
Termination is a resistor technique that dampens the
ringing of a transmission line and is necessary in high
speed logic systems. DEC PDP computers had bus terminators
on each line consisting of two resistors connected to
the line, one going to +5 the other to ground. The +5
resistor was necessary because the system was all open
collector logic and this resistor provided the high state
when the driving transistor was off. These resistors quash
out any ringing that would otherwise randomize the state
of the line when the system tries to read it. Without them
the clock that gates the data window open would have to
be much slower to allow the ringing to stop on it's own.
This would make for a slower computer.
>I've read in Horowitz & Hill that I should tie the outputs, then again that
>book seems less and less accurate as time goes on.
I don't see that. The sentence I see on page 486, second column,
at the top says that unused _inputs_ should be tied either high or
low. (2nd edition of the book). There may be some text about
"termination", perhaps of a tri-state bus, but this is not the
same as tying an output high or low. That can easily result in
a blown output transistor.
>The Harris CMOS Logic Selection Guide 1994, for the CD4000B series it says:
>"ALL CMOS inputs should be terminated. An exception can be made in the case
>of unbuffered NOR and NAND gates where terminating one of the series inputs
>to the proper polarity will not permit current flow caused by a floating
>input. Thus tying low one of the the inputs of an unbuffered NAND gate, or
>tying high one of the inputs of an unbuffered NOR gate will satisfy this
>So besides the previous exception, all the inputs should be tied. If the
>gate is unused, does it matter whether I tie them to Vdd or ground??
>Should they ever be tied to Vss??
It doesn't matter. There's almost no current in the gate circuit.
One of the transistors will always be biased on, the other off
no matter which way you do it. Do it whatever way is most convenient
for your physical layout.
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