[sdiy] CCD321 Analog Shift Register

[marmot1 at magma.ca]

Hi,
You use this formula for BBD delay time:

	delay (seconds) = (no. of stages)/(2 * clock rate)

So for 910 stages and 10 KHz clock, delay = about 45 milliseconds
For 910 stages and 20 MHz clock, delay = about 23 microseconds.
Bandwidth must be limited to less than (clock freq)/2 or else aliasing 
occurs. Practically, the BW is usually set at about (clock freq)/3.

So for 10 KHz clock, BW must be limited to less than 5 KHz.

BTW this is not a new chip - it's an old chip still in production.... 
Technically it's a CCD and not a BBD although similar things can be 
done.
Regards, Mike
 


Atom 'Smasher' wrote:
> 
> > http://www.fairchildimaging.com/main/linear_321.htm
> ====================================
> 
> S/N = 65db
> 
> is that any better than the old ones?
> 
> i'm still not sure how much time @ what cutoff freq could be had with 910
> stages.
> 
>         ...atom
> 
> ----------------Void-If-Detached----------------
> http://smasher.suspicious.org/fs1r  Yamaha FS1R
> 
>         "If you tell a lie big enough and keep repeating it
>          people will eventually come to believe it."
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