[sdiy] CCD321 Analog Shift Register

[marmot1 at magma.ca]

Hi Scott and List,
Take a look at www.fairchildimaging.com for a liitle bit of info on the 
chip - and a picture. My 1985 Fairchild CCD Imaging book shows 4 
versions of the CCD321 - the CCD321A-4 is tested for specs pertinent to 
audio, while the -1, -2, -3 versions are tested for specs pertinent to 
video delays and timebase compression/expansion. The CCD321A-4 is spec'd 
at 65 dB S/N ratio at  23 KHz BW and a clock freq of 50 KHz. Not great 
but similar to regular BBD's. The notes also say that the chip may be 
clocked below 10 KHz and above 20 MHz without damage, although the 
performance will not be as good. With a total of 910 stages, the range 
of delay times obtainable would be similar to what could be obtained 
with the Reticon SAD1024 (10 MHz max clock rate IIRC), although somewhat 
shorter delays could be obtained when run at full speed. Wonder if this 
was the mystery delay chip used in the Marshall Time Modulator? It might 
have been introduced earlier than the Reticon/Panasonic/ITT-Valvo BBD's.
Regards, Mike
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