[sdiy] CA3086 and CA3046?

[René Schmitz]

At 17:46 17.08.01 +0200, jh. wrote:
>> That depends on the rest of the circuit - when the output collector of the
>> expo runs into a virtual ground node for example, you'd be safe. The
>> transistors would never see more than -15volts. But when the collector is
>> going to a higher potential, the 20volts for Uceo might be exeeded.
>
>I suspect that's why Tom Oberheim used that strange T-divider instead of
>a single resistor for the ref current in the SEM's expo converters.
>Normally, virtual GND, but you can never know.

I've wondered about that, too. But then pin 13 is tied to -1.5V via that
1k/10k divider, so even when the collectors would hit 15V there would be a
margin of 3.5V. 

>Others were more adventurous. I think ARP has violated the pin13-most-
>negative-rule once. And in general, they knew what they were doing:
>Some of the most impressive circuits built from 3086 BJT and
>4007 MOSFET arrays.

Hmmm. In that circuit (if the Quadra is what you mean) the pin 13 is 
open. Now, what would happen if one simply can leaves pin 13 open? 
As I see it the insulating diodes between any two collectors would be 
back to back. And no current could flow. 
Would we only need to tie pin 13 to the lowest potential if the fifth 
transistor is actually used in the circuit? 
That could be an alternative interpretation of the datasheet. 

Cheers,
 René

-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159