[sdiy] CA3086 and CA3046?

[René Schmitz]

At 22:20 16.08.01 +0100, Christian wrote:
>The lowest DC potential in my circuit is the -15V supply rail. I am
>unsure if the transistor pair I am using will ever see this, but I
>might as well tie the substrate line to that rail just in case. Yes?


That depends on the rest of the circuit - when the output collector of the
expo runs into a virtual ground node for example, you'd be safe. The
transistors would never see more than -15volts. But when the collector is
going to a higher potential, the 20volts for Uceo might be exeeded.
(Chances are the chip will even survive this.) 
Putting pin 13 to -5V will be safer, you can use a voltage divider from the
negative supply to get that. 
The lowest potential in the expo circuit is at the emitters, they will be
usually arround -0.7V below GND.

Cheers,
 René


-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159