[sdiy] Non-uP trigger delay

[Grant Richter]

Use an EXOR gate with the two inputs feed from the clock square wave. Use a
lag processor on one input. Exors go high when the two inputs are different.
The pulse width will be set by the lag time. It's called a "double pulser"
and the output goes high for both the positive and negative going clock
transitions.
> 
> This example is fixed, but it would be nice if it was adaptive, ie
> as the clock changed BPM the second output would always
> happen at .5 of the time between the previous two events.
> 
> Am I making sense? Can it be done in analog/CMOS??
>