[sdiy] Non-uP trigger delay

[Thomas Hudson]

I have a feature I would like to add to a sequencer I'm building
and can't figure out how to do it without scrapping the design
and using a microprocessor. I need to create a pulse based
on half the time difference between the previous two pulses.

What I want to do is have a second output from the sequencer
that lags behind the primary output by 1.5 clocks.

Clock input is 200 ms.
Primary output plays stage one at x.
Primary output plays stage two at x+200 ms.
Secondary output plays stage one at x+300 ms.
Primary output plays stage three at x+400 ms.
Secondary plays stage two at x+500 ms.
...

This example is fixed, but it would be nice if it was adaptive, ie
as the clock changed BPM the second output would always
happen at .5 of the time between the previous two events.

Am I making sense? Can it be done in analog/CMOS??

Tomy