DIY Digital Synth

[Magnus Danielson]

From: Jim Patchell <patchell at silcom.com>
Subject: Re: DIY Digital Synth
Date: Tue, 19 Sep 2000 07:25:58 -0700

> 
> 
> jbv wrote:
> 
> > Your remarks confirm the feeling I had after reading both Xilinx & Altera datasheets
> > and application notes.
> >
> > I think I also remember reading somewhere that getting large internal data buses
> > (24 bits or more) between blocks can be a bit tricky...
> > And what about having large amounts of ROM & RAM in the design (I mean : not
> > as external chips, but inside the FPGA design) ?
> 
>     Large blocks of ROM/RAM are more of a problem in the Xilinx Parts (although I am not too
> sure about their Virtex Parts) than altera.

The Xilinx Virtex add dedicated RAM blocks and the followups to the Virtex
contains even more RAM blocks (on popular demand, from my firm among others).
The 4000 series (and its MANY versions) uses the LUTs as 16x1 bit memorycells
(which is really what they are anyway). In Virtex you may still do this, but
the additional dedicated RAM blocks is really good to have. Add external DRAM
for long samples/delay buffers and you have the basis for a seriously cool
DIY digital synth.

Half the troubles with FPGA is figuring out how to best make use of their
capabilities. For instance, you have alot of logic power at hand at the input
of any flip-flop, so it may not be wise to reuse an adder among diffrent
registers. One has to experiment and see how much space diffrent solutions take
and figure out alternative ways of solving things. This is in a way similar in
trying to dump of a few lines of mnemonics in some assembler hack in order to
have it take on less memory footprint.

> >
> > And is it easy to get a pipe-line structure ? Are basic blocks latched ?
> 
>     Pipelining is very easy with either family.  In the Altera library, you can even select
> how much pipelining you want.  The 16x16 multiplier can be 0 (no pipelining),1,.2 or 3 levels,
> so that you can trade off pipeline delays with speed.  Many of the other functions have
> pipeline options as well (including the dual port memories).

Each of the Xilinx CLB has a programable logic block at the input, using two
LUT (Look Up Tables) of 16x1 or 4-input-to-1-output, then some fixed logic with
some programability and then two flip-flops. So, pipelining comes virtually for
free since the flip-flops is just sitting there and doing nothing unless you
ask them to join the timing dance...

> >
> >
> > I guess another tricky step is to choose the right chip to work with, since the offer
> > of each company seems quite large...
> 
>     It is really more a choice of how many pins you want.  For Altera, the ACEX family is the
> low cost one.  Right now they seem to offer only 30K, 50K and 100K parts.  The machine I have
> block diagrammed on the web uses about 80% of the 30K part, although, it is always better to
> go one bigger.  For Xilinx, the Spartan series is the low cost solution.  If I remember
> correctly, the sizes availiable for that one are 5K, 10K, 20K and 40K.

Actually, I'd say that you must start with the size, if you expect the size of
a project to be at say 40k gates, you should have a margin so you use an FPGA
of at least 50k to 60k. Spare logic power translates into extra routing freedom
and this can allow you to get better timing predictions. Also, you can trade
speed with area, so by taking more area you can live with less speed most of
the times.

When you have settled for a size which is of interest, you can start to worry
about pin-count, logic levels etc.

One of the things that does annoy me is that you can't get hold of a good
synthesis, placement, route and bit generation packet which is suitable on a
private persons normal budget constraints. I'd love to use FPGAs at home for
many things, but the software budget problem is one thing, then they don't run
on a friendly operating system either... <sigh>

Cheers,
Magnus