DIY Digital Synth

[Jim Patchell]

jbv wrote:

> Your remarks confirm the feeling I had after reading both Xilinx & Altera datasheets
> and application notes.
>
> I think I also remember reading somewhere that getting large internal data buses
> (24 bits or more) between blocks can be a bit tricky...
> And what about having large amounts of ROM & RAM in the design (I mean : not
> as external chips, but inside the FPGA design) ?

    Large blocks of ROM/RAM are more of a problem in the Xilinx Parts (although I am not too
sure about their Virtex Parts) than altera.  Although, we need to define what Large is.  In
Xilinx parts (40xxE and Spartan), the basic ram block is 32x1 or 16x2.  But, you can make any
CLB (that is what they call their basic logic block for those unfamiliar) into a ram.  In
altera, the basic ram block size (for ACEX parts) is 2048x2/1048x4/512x8/256x16.  But, there
are fewer of them.  The smallest device only has three of these blocks, the largest 12.  The
logic cells in the Altera parts cannot be used for RAM/ROM.  So, if your memory requirements
are modest, say less that 30K bits, an FPGA will handle this.  This is the reason why the
Waveform Look Up Table will be external, because there is just no hope of putting it inside a
reasonable priced part.  Also, the size of the internal memories that I am using fit much
better into the Altera part than the Xilinx.

>
> And is it easy to get a pipe-line structure ? Are basic blocks latched ?

    Pipelining is very easy with either family.  In the Altera library, you can even select
how much pipelining you want.  The 16x16 multiplier can be 0 (no pipelining),1,.2 or 3 levels,
so that you can trade off pipeline delays with speed.  Many of the other functions have
pipeline options as well (including the dual port memories).

>
>
> I guess another tricky step is to choose the right chip to work with, since the offer
> of each company seems quite large...

    It is really more a choice of how many pins you want.  For Altera, the ACEX family is the
low cost one.  Right now they seem to offer only 30K, 50K and 100K parts.  The machine I have
block diagrammed on the web uses about 80% of the 30K part, although, it is always better to
go one bigger.  For Xilinx, the Spartan series is the low cost solution.  If I remember
correctly, the sizes availiable for that one are 5K, 10K, 20K and 40K.

>
>
> And could you tell us a bit more about cost ? And what about integrating the
> FPGA chip in some larger circuitry once it's programed ?
>

    Cost is not really all that bad.  Although, I can't remember exactly how much the Spartan
chips cost, $25->$30 seems to be the figure I remember for the Xilinx Spartan XCS40 (40K
part).  The Altera ACEX family is supposed to directly compete with the spartan chips, so I
would imangine their price range is about the same.

    How I have programmed the parts in the past is to load code right from the microprocessor
that goes along with the FPGA.  In the product I am working on right now, a pair of Xilinx
4010E's are loaded from a 68000.  I made a special 22v10 part that provides the interface
between the 68K and the FPGA's programming interface (these FPGA's are volatile, so you have
to program them every time you power up).  Other options include using the serial rom chips
that both Altera and Xilinx supply if you are either going stand alone, or the microcontroller
does not have the capacity to store the FPGA code.

>
> I really hope my questions aren't a drag...

    Not at all, this kind of stuff is fun.

>
> Thanks in advance...
>
> jbv

    -Jim