DIY Digital Synth

[jbv]

Hey boys & girls, here's more food for the brain !

Here is a block diagram of the digital synth I mentioned
in my previous post :
http://perso.wanadoo.fr/jbv.silences/DIY/Architecture.jpg

As explained before, it is heavily inspired from the 4C
by Di Giugno. This configuration was called 4U
(actually an extension of the 4C) and the 4X featured
8 similar boards for a total of 1700 TTL chips...
As you can see, it's pretty similar to a DSP...


First, the main blocks :

ALU : a regular adder / substracter.
Eventually, it can also perform boolean functions.

MUL : a rugular 16 x 16 -> 32 bits multiplier

WT : a ROM containing waveforms. A part of that
ROM is dedicated to an expo converter.

RAM : a large RAM space to store incoming audio
samples (possibly in stereo) for designing large reverbs
& delays. (a question regarding the ROM and RAM is
whether they can be squeezed inside the FGPA chip,
or if external ROM & RAM chips can be used...)

DM (data memory) : a small RAM space (8 K max)
used as temporary storage registers to store computation results .


Second, the 2 main buses and registers :

C bus & M bus : the whole thing is organized around t
hese 2 main buses used for data flow between basic blocks.

MA, MB, MX, MY... : input & output latches / buffers for
the basic blocks. The combination of these registers and the
2 main buses leads to a pipe-line architecture (for instance,
data can be loaded from M Bus into the input registers of
MUL while MUL is still performing the previous multiplication,
and while the result of an anterior multiplication is transfered from
MUL output register via the C Bus).


Third, adress and microprogram memories :

Adress memory adresses the cells of DATA memory
where temporary results must be read / written

Microprogram memory (the core of the system, the place
where the current running algorithm is actually stored)
controls all registers and main blocks :

- loads data from / to each main bus into / from input
& output registers

- selects which function to use in the main blocks
(in ALU for instance, it selects add or sub or boolean)

And last, clock & counter :

The clock that runs the whole system is a multiple of the
required sampling frequency. The algo is actually a main
loop. For instance, at 96 MHz and for a sampling frequency
of 48 KHz, 2000 micro-cycles (or microinstructions are available).
Of course, different algorithms can be stored in a larger adress
& uP memory space. Algos will be selected through the MSBs.


---------------------------

Here is an algorithm example : a digital oscillator with linear
interpolation (it uses 2's complement arithmetic). The pipe-line
structure is obvious here.
http://perso.wanadoo.fr/jbv.silences/DIY/Osc.jpg


---------------------------

As for Cellular Automata (mentioned in one of my previous posts),
here's an example of what can be done.
http://perso.wanadoo.fr/jbv.silences/DIY/CA.jpg

Let's say we have a one-dimension CA with 32 cells. By choosing
the adequate initial configuration and the adequate evolution rules,
successive steps of the system evolution can be calculated at a certain
rate (step 1, 2, 3, etc... in the schemo).
The transition of each cell from one step to the next ( 0 -> 1 or 1 ->
0)
can be interpolated, and the resulting slopes (in red on the schemo) can

be used to control various parameters in the digital synth : for
instance
the amplitude of each osc in a bank for additive synthesis, or the phase

offset of each osc. One should get rich cycling evolutions of the sound
spectrum.
Of course, 2 different CA settings can run at the same time, the 1st one

driving osc amps, and the 2nd one the phase offsets. The evolution rate
of each CA can be fixed, or driven by an external VC-LFO for instance...

Other similar applications could be a bank of tap-delays tuned in a
certain
way (as subharmonics, or according to a specific harmonic
progression...),
and the interpolated slopes from the CA could be used to drive the amp
of
each delay (or the feed-back ratio of each delay into the input signal).

I feel that interesting results can be achieved with a perc loop for
instance.
Another idea : the tap-delays could be replaced by a bank of
pitch-shifters
tuned in a certain way...


So far, I don't know if the CA machinery can be included in the FPGA
chip,
or if an external uC should be used, with the slopes sent as input data
to the
digital synth kernel...

jbv