Cross Product Sub Octave Module

[Martin Czech]

:::http://www.spiritone.com/~8brain/xproductflat.gif

Ok, rant mode ON ;->

The drawing does not tell what supplies are used for the opamps.  I guess
V+ and -(V+), because any opamp could tollerate that.  Few can go with
unipolar supply and full swing output.

So I'm again guessing...

I see that no hysteresis is used for the comparators.  I see that the
comparator output is not pushed to speed with a schmidt trigger of the
same logic family it is going to drive.  I see that no provisions are made
for a proper CMOS input level, but I see suspicious 470 Ohm resistors,
which lead me to the conclusion, that the CMOS ESD protection is used
as clamping device for the negative level of the comparator.

13V/470 Ohm= 27 mA!

O o  o o!

Our costumers try to save on every penny they can, and so they often try
to abuse our I/Os for clamping purposes. We are very sad to tell them,
that our VLSI ICs are not very happy with this (I know, because the I/O
libs are mine ;->) , but we often get  the reply: "it works".

Yes, but one day there may be a lot with far away bipolar parameters,
but still in spec. And there's a lot of supply bouncing as well, and
it is hotter than usuall and the regulator is at +10%. The applied dc
clamp current makes the margin small, and then CMOS does what it does:
LATCHUP. The alu lanes boil away so quickly, you won't even notice. And
then the parts come back to quality inspection, "unknown failure". But
we'll find out. And we'll look at their pcbs, and we say: "We told
ya". Way out of spec, way out of absolute maximum ratings.

And the customer crys and whines, now he has to change all pcbs, and
he tells us that our ICs are not reliable.

That's why such action is strictly prohibited in our data sheets.


In our case things are much worse, because a CD4520 can be obtained
from more then 10 fabs, and I guarantee that all are a bit different
with respect to latchup sensitivity.

Some circuits do not apply dc current to the ESD structures, but spikes.
Very often that can be found in differentiating circuits with caps
which make some input go negative. Even worse, because now the current
is not propperly limited and most people even don't know why the circuit
freaks out. "but it works". Ok.

Some more ranting:

Any type of logic will be unhappy if the clock slopes are flat,
i.e. > some 50ns, or the typicall INTERNAL inverter delay in this case.
Especially these CD4xxx families, because internally there must be digital
differentiators in order to select rising or falling clock edges, these
circuits need fast slopes. Most opamps slew not fast enough.


Every now and then, I see schematics where some clock is derived
in this or some other way. Someone did try to save a penny.

Why? The 311 (e.g.) is such a nice part, it avoids much of this trouble.
It's stable (good layout provided), fast, enables you to have
analog and digital supply treated in a proper way, allows for 
good digital levels and slopes, and the input stage is quite accurate.
It's simply made for this purpose. A 741 isn't.



Still some more ranting:

I wonder what or/exor gates would give in place of the 4081.
EXOR should sound cool.


Now I'll shut up, rant mode off ;->>

m.c.