SID vs. NMOS tech (fwd)

[>>>marjan<<<]

> NMOS design (8580 is HMOS). In the filter part, biased NMOS inverters
> are used as op-amps and simple NMOS FETs as voltage controlled resistors
> :-O. Because of this, the filter doesn't seem to match any known filter
> responses ;-). It's indeed very nonlinear; its response highly depends
> on the amplitude of the signal that is fed through the filter.
> 

EDP Wasp used logic CMOS gates as in linear operaton as opamps.
FET part shouldn't affect the sound, rather response to VC, if they
are mismatched filter cores may track unperfectly.

Read SidTech pages http://stud1.tuwien.ac.at/~e9426444/index.html
as it has the best info about SID. Check also it's inventor's 
article there.

Overall SID VCF was wimpy (agreed by inventor too) because of then
low integration and not so good NMOS tech process.
Later chip in HMOS had better "opamps" so they matched and didn't
"leak" so there was better ("stronger") resonance available,
which original SID lacked (well some at least as chips differed
from piece to piece).

> The current implementation models an 'ideal' two-integrator-loop
> biquadratic filter with a measured cutoff-to-register_value mapping.
> 
> I'm aiming to model the filter part in a simulator, but I'd definitely
> need some help for increasing my effectivity ;-). I'm not much familiar
> with FETs; I used to know their overall features, but have certainly
> never digged deep into FET based analog tech.
> 

I think you can reach Yannes via mail. He should know the best.
But also check patent for sid US4677890, there was (I think, not sure
thou) mosfet model of inverters.



> They would be needed, since the filter is an analog circuit. It seems
> like the FETs get overdriven almost everytime during normal operation;




> the filter doesn't act as expected except the lowest signal levels (not
> to mention, that the OSCs have DC offsets, helping the FETs going out of
> their operating point even easier). Resistance, the typical gate opening

There IS constant DC current in NMOS ccts in the first place.
 
> voltage and so on. Typical gate-capacitance (seems like it's
> significant) and its behaviour in function of the gate voltage.
> 
> - How does a Commodore MOS inverter look like _exactly?

There are two standards. If you take your fact that it goes to
saturation
almost every time it's probably basic one:
all subs to gnd, lower mf gate is input, s to gnd, d is out and
connectad
to s of upper "dummy" mf acting as active load with gate and d connected
to vdd.
But as sid has two DC suppply (9 and 12v) I gues it's using somewhat
better
scheme with all the same topology as previous one except upper mf has
gate
connected to some ref voltage (vgg) smaller than vdd (it's unsaturated
active load but it's just a translation not sure what is standard term).
you have here lerger Id and lareger logic amplitude (logic 1 is higher),
problem is it uses larger Si area (and small space left on the chip
was mentioned by inventor). There is better solution with mf with
fixed channel (?) for upper load but I doubt they used it then.

Try some textbook for detailed NMOS tech.

> 
> - Is it possible to create real (linear) resistors in NMOS
> manufacturing?
> 

In some small region of operation perhaps.



Cheers,


marjan