BBD-MN3010 and MN3011- is a MN3101 clock necessary?

[Haible Juergen]

	>Once again: 

Thanks for writing this again - sorry I had missed it.
I admit I have spent less thoughts on the actual mechanism of performance
degradation than you did. What you're writing about overlap causing
leakage, reducing level and therfore decreasing SNR sounds reasonable.
You're probably right about the spikes, too. 
In the end you can filter the spikes with a good filter, of course, so the
leakage would be the worse problem I guess.

	>My approach would be a totally different one: I'd sample the output
with a
	>good/fast S&H in the middle of the clock pulse.

I think I saw this somewhere. I had no idea why there was an extra S&H
stage, but now as you say it this could be th eexplanation.
Of only I knew *where* I've seen it. Crumar Performer maybe. Not sure.

I took a brief glance at the SRS-56 circuit (very brief - 30 seconds before
I went to work), and what I think I saw is this:

4 NAND gates form a HF VCO.
One half of a JK-FF to create the symmetrical clock.
Other rhalf of JK-FF connected as monoflop to create the gap.
(and a trimpot to adjust the exact gap time - fits in your theory !)
2 NAND gates to mask the symmetrical clock during the gap time.
(as suggested in TDA1022 data sheet)
Two high current drivers (complementary emitter follower, "class C
amplifier", 10 Ohm current limiting resistors at collectors.

More interesting circuit details: NE570 companders with quite some
external components to improove the 570's performance.
Discrete 6-pole filters at BBD input and output.

JH.