BBD-MN3010 and MN3011- is a MN3101 clock necessary?

[Doug Ferrell]

Ah, the magic of XOR...  I'm not seeing the 3-input XOR solution.  I can see
a 3-gate fix (2 AND and 1 XOR) after the counter:

Let q and q' be the complementary outputs of the counter.

The non-overlapping (on the positive side) outputs, Q and Q', are derived as
follows:

Q = q AND (q XOR q')
Q' = q' AND (q XOR q')


Wait...I think I see where Theo's going now.  By using several output taps
from the counter it should be easy to remove the overlap with some simple
logic.  My solution produces a fixed and small gap while the multi-tap one
will produce a gap which dependent on the clock frequency driving the
counter.  Interesting.  A 4024 would allow smaller gaps to be achieved.

Doug

p.s.  Am I the only one here with a deep fascination with XOR and it's uses?


> -----Original Message-----
> From: owner-synth-diy at node12b53.a2000.nl
> [mailto:owner-synth-diy at node12b53.a2000.nl]On Behalf Of Theo
> Sent: Thursday, May 04, 2000 10:02 AM
> To: Mike I.; synth-diy at node12b53.a2000.nl
> Subject: Re: BBD-MN3010 and MN3011- is a MN3101 clock necessary?
>
>
> What about a 4017 and some 3 input exor gates.
> (diodes may work as well)
>
> Cheers Theo
>
> ----- Original Message -----
> From: Mike I. <mirwin1 at istar.ca>
> To: <synth-diy at node12b53.a2000.nl>
> Sent: Thursday, May 04, 2000 5:59 PM
> Subject: Re: BBD-MN3010 and MN3011- is a MN3101 clock necessary?
>
>
> > Finally got a dual-trace scope. That done, one of the first
> things to
> > look at was the outputs of the MN3102 clock chips in two
> analog delay
> > units. The first unit had an MN3102 driving an MN3207
> 1024-stage NMOS
> > BBD, the second unit had a MN3102 driving an MN3205
> 4096-stage NMOS BBD.
> >  Both units showed leading-edge and trailing-edge windows
> (about 250
> > nanoseconds) where the clock lines were simultaneously low.
> This 250 nS
> > window time stayed constant as the frequency was swept from
> 12 KHz to
> > 200 KHz. A 9 volt power supply was used. Rise and fall
> times were about
> > 30 - 50 nS. The MN3205 capacitance (2800 pF) slowed the
> clock rise and
> > fall times, but the full voltage swing was still there. The MN3102
> > datasheet has a block diagram which indicates that the chip
> contains an
> > oscillator, divide by two circuit, waveshaper, output
> buffers, and bias
> > generator, but does not say much about the waveshaping. The
> accompanying
> > data sheets for the BBD chips indicate that they should be
> driven with a
> > biphase clock where the overlap between the two waveforms
> ("crossover"
> > on the data sheet) occurs at zero volts to a maximum of 0.3
> * (clock
> > high voltage). (True non-overlapping clocks would have a waveform
> > crossover at zero volts) . Next, took a look at the outputs
> of a CD4013B
> > driving an SAD1024 and saw the overlap occurring at half the supply
> > voltage, as expected. So, IF it is desirable that a real
> non-overlapping
> > clock be used, the MN3102 (and probably also the MN3101)
> are an easy way
> > to do it. An earlier message in this thread suggested that
> very brief
> > overlap might be better than no overlap in maximizing BBD
> performance.
> > Mike I.
>