Saga of the uP developer

[Fraser, Colin J]

> -----Original Message-----
> From: Tim Ressel [mailto:Tim_R1 at verifone.com]
> Sent: 27 June 2000 01:57
> To: synth-diy at node12b53.a2000.nl
> Subject: RE: Saga of the uP developer
> 
> 
> Compared to this, a uP adsr seems child's play! Except the 
> processor may not be
> fast enough for 1mS 2-channel updates <twitch>...

On the subject of software EGs, I really like the hybrid appoach used in the
Moog Source.
The CPU sends two voltages to an expo slew circuit, with a comparator input
back to the CPU to tell it when the peak value is reached (end of the attack
phase).
The different rate and target voltages for the slew circuit are output by
the CPU based on the patch settings, gate and comparator signals.
This has a couple of advantages over a fully software ADSR - true expo
curves, and a tiny processor load so you could use one CPU for multiple EGs
(or indeed all the other functions of the synth CPU as in the Source). 
Add a window comparator and you could easily do multi-stage rate/target type
envelopes.
Another entry on my rainy day list...

Colin f