A source of error?

[jorgen.bergfors at idg.se]

Hi all.
I just built the sample and hold from René Schmitz page (http://www.uni-bonn.de/~uzs159/sah.html).
When doing the board layout, I realized that the circuit diagram symbol for JFETs doesn't tell which is source and which is drain.
Is there a convention for this? I tried it both ways, and it didn't seem to matter. Does it make a difference? If not, why do they have different names?
Another problem with this circuit was that the response was very non-linear. But when I lowered the 1M resistor between gate and source (or is it drain?) to 100k, it became perfectly linear. Comments? René?
Also it doesn't seem to hold voltages below -8 volts. The voltage just jumps back to around -8 volts if the sampling rate isn't fairly high. Any ideas?

/Jorgen
 P.S. René, can you please write 4k7 instead of 4.7k? In the MS20 VCF schematic it is impossible to tell wether resistors are 1.8k or 18k.